1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel having a built-in driving circuit.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) device can be used as a display monitor for a television and a computer. In an LCD device, light transmittance of a liquid crystal is controlled using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type. A driving circuit is provided for driving the liquid crystal display panel.
FIG. 1 is a block circuit diagram showing a configuration of a related art liquid crystal display device. Referring to FIG. 1, a related art LCD device includes a liquid crystal display panel 13 having (m×n) liquid crystal cells Clc arranged in a matrix, m data lines D1 to Dm and n gate lines G1 to Gn crossing each other and thin film transistors TFT provided at crossing of the data lines and the gate lines, a data driving circuit 11 for applying a data to the data lines D1 to Dm of the liquid crystal display panel 13, and a gate driving circuit 12 for applying a scanning pulse to the gate lines G1 to Gn.
The liquid crystal display panel 13 is formed by joining a thin film transistor substrate to a color filter substrate. The thin film transistor substrate is provided with a thin film transistor array. The color filter substrate is provided with a color filter array. a liquid crystal layer is provided between the thin film transistor substrate and the color filter substrate. The color filter substrate is provided with a black matrix, a color filter and a common electrode. Polarizers having polarization axes perpendicular to each other are respectively attached onto the thin film transistor substrate and the color filter substrate of the liquid crystal display panel 13, and an alignment film for determining a free-tilt angle of the liquid crystal is further provided on the inner side surface coming in touch with the liquid crystal layer.
The data lines D1 to Dm and the gate lines G1 to Gn provided at the thin film transistor substrate of the liquid crystal display panel 13 cross each other perpendicularly. The thin film transistor TFT provided at each crossing of the data lines D1 to Dm and the gate lines G1 to Gn applies a data voltage supplied via the data lines D1 to Dn to a pixel electrode of the liquid crystal cell Clc in response to a scanning pulse from the gate line G1 to Gn. The liquid crystal cell Clc rotates a liquid crystal having a dielectric anisotropy in response to a potential difference between a data voltage supplied to the pixel electrode and a common voltage supplied to the common electrode to thereby control light transmittance. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is provided between the pixel electrode and a pre-stage gate line or between the pixel electrode and a common line (not shown), thereby holding constant a data voltage charged in the liquid crystal cell Clc. The data driving circuit 11 converts an input digital video data into an analog data voltage using a gamma voltage. The data driving circuit 11 applies the converted analog data voltage to the data lines D1 to Dm. The gate driving circuit 12 sequentially applies a scanning pulse to the gate lines GL1 to GLn to thereby select a horizontal line of the liquid crystal cell Clc to be supplied with a data.
FIG. 2 is a block diagram showing a configuration of a gate driving circuit shown in FIG. 2 according to the related art. As shown in FIG. 2, the gate driving circuit 12 includes a shift register having an n-number of stages, 1st to nth, connected in a cascade to an input line of a start pulse Vst to sequentially supply a scanning pulse to gate lines G1 to Gn. The 1st to nth stages shown in FIG. 2 are commonly supplied with a clock signal CLK, along with high-level and low-level driving voltages VDD and VSS, and with a start pulse Vst or an output signal of the previous stage. The 1st stage outputs a scanning pulse to the first gate line GL1 in response to the start pulse Vst and the clock signal CLK. Further, the 2nd to nth stages sequentially outputs a scanning pulse to the second to nth gate lines G2 to Gn, respectively, in response to an output signal from the corresponding previous stage and the clock signal CLK. In other words, the 1st to nth stages have the sane circuit configuration. At least two clock signals having different phases are used for providing the clock signal CLK.
FIG. 3 is a detailed circuit diagram of the 1st stage of the related art gate driving circuit shown in FIG. 2. Referring to FIG. 3, the 1st stage includes an output buffer and a controller. The output buffer includes a pull-up NMOS transistor NT6 and a pull-down NMOS transistor NT7. The pull-up NMOS transistor NT6 output a first clock signal CLK1 to an output line under control of a Q node. The pull-down NMOS transistor NT7 output a low-level driving voltage VSS to the output line under control of a QB node. The controller includes NMOS transistors NT1 to NT5 for controlling the Q node and the QB node. The 1st stage is supplied with high-level and low-level voltages VDD and VSS, and a start pulse Vst. Four clock signals CLK1 to CLK4 with different phases are available, three of which, CLK1, CLK3 and CLK4 are supplied to the 1st stage.
FIG. 4 is a driving waveform diagram for the 1st stage shown in FIG. 3. Referring to FIG. 4, during a first time period A, the NMOS transistors NT1 and NT2 are turned on by high-level voltages from the start pulse Vst and the fourth clock signal CLK4 to thereby pre-charge the high-level voltage of the start pulse Vst into the Q node. The pull-up NMOS transistor NT6 is turned on by a high-level voltage pre-charged into the Q node to thereby supply a low-level voltage from the first clock signal CLK1 to an output line, that is, the first gate line G1. At this time, the QB node is driven low by the NMOS transistor NT5, which is turned on by the start pulse Vst. Thus, the NMOS transistor NT3B and the pull-down NMOS transistor NT7 are turned off. The NMOS transistors NT3A and NT4 also are turned off by a low-level voltage from the third clock signal CLK3.
During a second time period B, the NMOS transistors NT1 and NT2 are turned off by low-level voltages from the start pulse Vst and the fourth clock signal CLK4, so that the Q node floats to a high state, while the pull-up NMOS transistor NT6 remains on. Then, a high-level voltage from the first clock signal CLK1 bootstraps the Q node due to a parasitic capacitance caused by an overlap between the gate electrode and the drain electrode of the pull-up NMOS transistor NT6. Thus, the Q node voltage jumps higher to turn on the pull-up NMOS transistor NT6, thereby rapidly supplying a high-level voltage from the first clock signal CLK1 to the first gate line G1.
During a third time period C, the NMOS transistors NT1 and NT2 are turned off by the low-level voltages from the start pulse Vst and the fourth clock signal CLK4, so that the Q node floats to a high state, while the pull-up NMOS transistor NT6 remains on. Thus, the pull-up NMOS transistor NT6 remains on to thereby supply a low-level voltage from the first clock signal CLK1 to the first gate line G1.
During a fourth time period D, the NMOS transistors NT3A and NT4 are turned on by a high-level voltage from the third clock signal CLK3, so that the Q node is discharged into a low-level voltage while the QB node is charged into a high-level voltage. The high-level voltage at the QB node turns on the NMOS transistor NT3B to accelerate the discharge of the Q node, and the pull-down NMOS transistor N7 is turned on to supply a low-level voltage to the first gate line G1.
During a fifth time period E, the NMOS transistors NT4 and NT5 are turned off by a low-level voltage from the third clock signal CLK3. The QB node floats to a high state. The pull-down NMOS transistor N7 remains on to supply a low-level voltage to the first gate line G1. Further, the pull-down NMOS transistor NT7 remains on continuously until the high-level voltage of the start pulse Vst is supplied.
FIG. 5 is a schematic plan view of a liquid crystal display panel with a built-in gate driving circuit according to the related art. Referring to FIG. 5, the related art gate driving circuit having the above-mentioned configuration is built in a liquid crystal display panel 10 by using an amorphous silicon thin film transistor. A size of an output buffer of each stage, for example, the pull-up and pull-down NMOS transistors NT6 and NT7, is set to have a very large value due to a low mobility. This is due to the fact that the scanning pulse is directly applied via the output buffer, as described above, and that a channel width of the output buffer has a large impact on the life of the liquid crystal display panel 10. According to a design constraint, the output buffer must have a channel width of more than thousands of millimeters (mm). The channel width can be more than ten thousands of microns (μm) in order to drive a medium-to-large liquid crystal display panel of more than ten (10) inches. For this reason, an area occupied by the built-in gate driving circuit 30 must be enlarged. However, product standardization limits how much the circuit area can be enlarged within the non-display area. Accordingly, a bi-directional driving method has been proposed, which provides first and second gate driving circuits 30 and 40 at each outer side of a display area 20 as shown in FIG. 5 to concurrently drive the gate lines of the display area 20 at each side thereof.
FIG. 6 is a plan view of the related art liquid crystal display panel with a built-in gate driving circuit of FIG. 5. Referring to FIG. 6, the i-th gate line Gi concurrently receives scanning pulses from the ith stage 32i from the first gate driving circuit 30 and the i-th stage 42i from the second gate driving circuit 40, thereby applying a data signal on the data line D, via the thin film transistor TFT connected to the gate line Gi, to the pixel electrode 44. Next, the (i+1)-th gate line Gi+1 is driven by scanning pulses concurrently received from the (i+1)-th stage 32i+1 from the first gate driving circuit 30 and the (i+1)-th stage 42i+1 from the second gate driving circuit 40. As shown in FIG. 6, each of the stages 32i and 32i+1 from the first gate driving circuit 30, or each of the stages 42i and 42i+1 from the second gate driving circuit 40, includes an output buffer 54 having pull-up and pull-down transistors NT6 and NT7, and a controller 52 having transistors NT1 to NT5 for controlling the output buffer 54. Further, a line on glass (LOG) area 50 is provided with a plurality of LOG-type signal lines for supplying a plurality of clock signals and power signals. The LOG area 50 is located at the outer portion of the stages 32i and 32i+1 of the first gate driving circuit 30 and the outer portion of the stages 42i and 42i+1 of the second driving circuit 40. Also, a sealant (not shown) is coated onto the outer portion of the LOG area 50 for joining the thin film transistor substrate with the color filter substrate. Since the sealant contains a glass fiber that can cause corrosion when in contact with food, the first and second gate driving circuits 30 and 40 and the LOG area 50 are located at the inner side thereof so that they do not overlap with the sealant.
Therefore, a line width of the circuit area at which the first and second gate driving circuits 30 and 40 can be provided is limited to the non-display area at the inner side of the sealant. A length for one stage is limited to one liquid crystal cell. Thus, the size of the output buffer 54 is not enlarged. Accordingly, a scheme capable of enlarging the area of the built-on driving circuit is needed.